This invention relates to surface treatment of semiconductor device surface--particularly to the surface planarization of integrated circuits.
An important consideration in the fabrication of submicron integrated circuits (IC) is planarity. With dimensions at submicron levels and with increased number of metal interconnection layers in very large scale integration (VLSI), the metal thinning that can occur over steep topographies becomes very serious problems. The yield and reliability can be adversely affected. Chemical-mechanical polishing (CMP) has been widely used to planarize the surfaces of high density integrated circuits.
In the CMP process, a microabrasive material is applied and rubbed by a specialized polishing pad, which uniformly removes the top surface of films that have been deposited on the wafer. There are, however, several issues affecting the adoption of CMP. An overriding difficulty is wafer throughput. Ideally, the process would involve a single-pass system capable of reliable production runs. Lack of an endpoint system for measuring oxide film thickness during polishing is another problem. Contamination is still another issue. As a result, the process tends to weaken the underlying oxide. To date, the CMP is an extremely difficult process. Yet, it is the only available method. The need for global flatness remains not satisfactorily fulfilled.